Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

PLL Merging

I have two designs very similar, both instantiate one PLL, two ALT_LVDS_TX and two ALT_LVDX_RX. Design A, drives the output of the PLL to a pin, design B does not. For design A, Quartus g...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Each PLL can have only two clock inputs. If you have different clock sources, then the system will use more PLL.