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Altera_Forum
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16 years ago

PLL megacore probs.build my own??

Hi all, I want to implement a PLL that will lock onto & track an incoming signal of about 30KHz and output a multiple of that locked frequency. I tried using Quartus's PLL megacore function but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You can use the phase accumulators most significant bit as digital clock :)

P.S.: Or more appropriate for a synchronous design, generate a clock enable on it's rising edge for one input clock cycle.