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Altera_Forum
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16 years ago

PLL megacore probs.build my own??

Hi all, I want to implement a PLL that will lock onto & track an incoming signal of about 30KHz and output a multiple of that locked frequency. I tried using Quartus's PLL megacore function but...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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The noise/jitter,therefore is not particularly specified.

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To mention an obvious fact. Above a certain input signal jitter, no meaningful PLL operation can be expected. A phase noise analysis of the input signal can answer the question.

Generally, I hear from your answer, that a time discrete 5 MHz clock based .e.g. on a 40 or 80 MHz system clock can be acceptable. This would basically allow an all-digital PLL solution.