PLL megacore probs.build my own??

The incoming signal to be locked onto is a correlator output. Basically two siganls are correlated and the output is a signal with periodic peaks where the two signals are the same. I need to lock onto the frequency of those peaks and multiply that frequency with 160 in order to sample.

Its a frame and symbol synchronisation opearation, where the frames are at the 31.250KHz frequency & the symbols at 5MHz.

the output frequencies are therefore clocks with 50% duty ratio & the lock in time/settling time can be anything (obviously, the quiker the acquisition the better, so tradeoffs will have to be made between the settling time and the allowable noise/jitter). The noise/jitter,therefore is not particularly specified.