Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHi again people.
Thank you for your replies. I struggled the whole of today to implement the PLL in Quartus but I couldnt get it right. one of my problems was that I have no control over the output bit width of some of the megacores (like te filter). The NCO also determines the input bit width according to my specs & this causes there to be a mismatch between the subsystems. Would the NCO be able to output a 5MHz & 20MHz singal from a locked 31,250KHz signal anyway?