Forum Discussion
Altera_Forum
Honored Contributor
16 years agoLooking at the PLL hardware specification clarifies, that it can't use a 30 kHz reference clock. Without going too deep into details, it's simply impossible for a PLL with a 0.5 to 1 GHZ VCO range.
Designing "your own" PLL is actually an option. But an low frequency equivalent to the FPGA PLL would be rather a basic all digtal PLL than a NCO design dealing with digitized waveform. Although the latter is also feasible, of course.