New Contributor
Frequent ContributorHi @Norick
May i know did you see the warning using earlier attached design?
Or better, if you can provide me a simple design that shows the error, i can confirm it on my end.
Normally, you will see this warning when you use normal IO instead of dedicated clock pin.
Im not sure why you are seeing those errors if you are already using dedicated pins. I hope you can test the design, and let me know the results. Then only i can help further.
New ContributorHello
attached I send you a simple design with following warning messages:
Warning (15055): PLL "PLL_Main:PLL_Main_inst3|PLL_Main_altpll_0:altpll_0|PLL_Main_altpll_0_altpll_hl92:sd1|pll7" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
Info (15024): Input port INCLK[0] of node "PLL_Main:PLL_Main_inst3|PLL_Main_altpll_0:altpll_0|PLL_Main_altpll_0_altpll_hl92:sd1|pll7" is driven by FPGA_CLK1~inputclkctrl which is OUTCLK output port of Clock control block type node FPGA_CLK1~inputclkctrl
Warning (15058): PLL "PLL_Main:PLL_Main_inst3|PLL_Main_altpll_0:altpll_0|PLL_Main_altpll_0_altpll_hl92:sd1|pll7" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
Warning (15064): PLL "PLL_Main:PLL_Main_inst3|PLL_Main_altpll_0:altpll_0|PLL_Main_altpll_0_altpll_hl92:sd1|pll7" output port clk[0] feeds output pin "clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Question:
Thanks
