pll input ports as unconstrained input ports with TimeQuest

The system contains a Cyclone II FPGA, SDR SDRAM and some other components. There is one crystal oscillator connected to the four dedicated pll input FPGA pins.

The configuration includes 4 plls (the input ports called clk1, clk4, clk8, clk12) and a sopc module, with one of the pll outputs c0 as clk. The 4 plls' outputs c2 run 4 dedicated pll output FPGA pins (e.g. one called SCLK, the clock for the SDRAM with -144 degree phase shift).

Now I'm trying to constrain all ports etc. for the TimeQuest analyzer. I'll try to show the problem for the sdram part only.

According to the documents I found, I wrote the following SDC file content:

# #########################################

# clocks

create_clock -period 37.037 -name clk_in_27MHz [get_ports {clk1 clk4 clk8 clk12}]

...

derive_pll_clocks

# the messages in the console are

# Info: create_generated_clock -source inst3|altpll_component|pll|inclk[0] -name inst3|altpll_component|pll|clk[0] inst3|altpll_component|pll|clk[0]

# Info: create_generated_clock -source inst3|altpll_component|pll|inclk[0] -phase 90.00 -name inst3|altpll_component|pll|clk[2] inst3|altpll_component|pll|clk[2]

# Info: create_generated_clock -source inst4|altpll_component|pll|inclk[0] -multiply_by 4 -name inst4|altpll_component|pll|clk[0] inst4|altpll_component|pll|clk[0]

# Info: create_generated_clock -source inst4|altpll_component|pll|inclk[0] -multiply_by 4 -phase -144.00 -name inst4|altpll_component|pll|clk[2] inst4|altpll_component|pll|clk[2]

# Info: create_generated_clock -source inst2|altpll_component|pll|inclk[0] -name inst2|altpll_component|pll|clk[2] inst2|altpll_component|pll|clk[2]

# rename clks

set sdramclk inst4|altpll_component|pll|clk[2]

...

# clock outputs

create_generated_clock -name sdram_clk_pin -source $sdramclk -offset 0.5 [get_ports {SCLK}]

...

# #########################################

# slow asynchronous I/Os

# reset

set_false_path -from [get_ports {GDCRST}]

...

# #########################################

# sdram ports

# from the datasheet

# max input delay (max clock to out = access time from clk) 6.0ns

# min input delay (min clock to out = data out hold time) 3.0ns

# max output delay (min setup = cs,ras,... setup time) 2.0ns

# min output delay (min hold = cs, ras,... hold time) 1.0ns

# common pcb routing delay 0.5ns +/- 0.1ns (evtl weniger, nur ca. 1-2cm, nicht 10cm)

set_input_delay -clock sdram_clk_pin -max 6.6 [get_ports {DQ[*]}]

set_input_delay -clock sdram_clk_pin -min 3.4 [get_ports {DQ[*]}]

set_output_delay -clock sdram_clk_pin -max 2.6 [get_ports {/CAS /RAS /WE /CS A[*] BA* CKE DQM* DQ*}]

set_output_delay -clock sdram_clk_pin -min -0.6 [get_ports {/CAS /RAS /WE /CS A[*] BA* CKE DQM* DQ*}]

....

# #########################################

After compilation, creating timing netlist, creating the above mentioned sdc file, reading sdc file, updating timing netlist, running 'report unconstrained paths' it shows:

- clk1, clk4, clk8, clk12 as unconstrained input ports

- SCLK ... as unconstrained input port paths

There are no unconstrained clocks reported.

It seems the part between the ports clk1... and the pll input is missing, although the documentation says 'you do not have to generate the base clock on the input clock pin of the pll' in the section about derive_pll_clocks.

Please don't suggest to add the '-create_base_clocks' argument, since I'm using Quartus II 6.1. So, how did they do it in those former times?

What did I get wrong about this constrainings? Is 'set_clock_groups' missing? Is one base clock not enought for 4 FPGA clk inputs? I tried several things in the sdc file, but I'm running out of ideas. So any help will be appreciated.