pll input ports as unconstrained input ports with TimeQuest

Here's the whole content of the sdc file:

# #########################################

create_clock -period 37.037 -name my_clk -add [get_ports {clk}]

derive_pll_clocks

# or else instead of the last line (causing the same result)

# create_generated_clock -name sys_clk -source [get_ports {clk}] -multiply_by 4 [get_nets {inst2|altpll_component|_clk0}]

# create_generated_clock -name sdram_clk -source [get_ports {clk}] -multiply_by 4 [get_nets {inst2|altpll_component|_clk2}]

# and variations of the last line:

# create_generated_clock -name sdram_clk -source [get_ports {clk}] -phase -144 [get_ports {SCLK}]

# create_generated_clock -name sdram_clk -source [get_nets {inst2|altpll_component|_clk2}] [get_ports {SCLK}]

# virtual clock for host interface, maybe period too small

create_clock -period 1000.000 -name virt_jtag_clk [get_ports {altera_internal_jtag*}]

# #########################################

# slow asynchronous I/Os

# reset

set_false_path -from [get_ports {/GDCRST}]

# jtag

set_false_path -from [get_ports {altera_internal_jtag*}]

set_false_path -to [get_ports {altera_internal_jtag*}]

# #########################################

The project and the report unconstrained paths result is shown in the pdf. Just that one single added output port seems to cause the strange behaviour?!?