Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

PLL input from non-dedicated clock pin

Hello all,

I've struck with a simple problem and I'm almost nearing the wall in terms of options.

I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've to generate a divide-by-2 clock and I read in the forum the best way is to use PLL.

PLL can be driven from Global clock lines or dedicated clock pins. So, I instantiated a ALTCLKCTRL megafunction to route the pin on global clock line and then use that as input for the PLL. But, I still get the same error

Error: Can't place Top/Bottom or Left/Right PLL "sclkpll:u7|altpll:altpll_component|sclkpll_altpll:auto_generated|pll1" -- I/O pin ClkIn (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device

Here is the code for the same

sclkctrl u1 (
	.inclk(ClkIn),
	.outclk(ClktoPLL));
sclkpll u2 (
	.inclk0(ClktoPLL),
	.c0(ClkfromPLL));

Its almost like the ALTCLKCTRL block has been removed by optimization. Can you suggest any alternatives?

Thanks,

Gopal

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I've to run module A at half of the Clk2 frequency. I've not depicted the divider because I'm not sure which is the best way to go about

    1. Ripple clock divider

    2. Gate the Clk2 before module A (Now there will be 2 enables, one outside module A, one is already inside, I hope it will not be an issue)

    I've already tried 1 (saw some hold slack issues) and will give 2 a shot.