PLL generated clocks and timing constraints

Thinking about this some more, I'm concerned that your PLLs will talk correctly. For example, if you have 4 devices all fed with an 80 MHz clock that then create a 260MHz clock, the output clock will "align" with the input clock every 4th cycle(I think, please double check). But there is no guarantee this alignment will occur in sync across the 4 PLLs. For example, the period is ~3.846ns. So making up a theoretical time 0ns that the first PLL locks up with, it will have edges at 0ns, 3.846, 7.69, 11.538, etc. But another PLL may align with the input clock at time 8.5ns, so it will have edges at that are not "off" from the other PLL.

I did a sample design to fix this, but it requies the PLLs sending out the faster clock and then we divide it down in the altclkctrl block:

http://www.alteraforum.com/forum/showthread.php?t=1473&highlight=pll

Naturally, we can't send out a 13*80MHz clock to do this, as the clock trees don't run that fast.

My thoughts would be to:

a) Run at 3x, or 240MHz, so the output clocks align with every edge of the input clock and the problem goes away. (Theoretically you could do a 4x too)

b) Have one device's PLL create the clock and use that to distribute that across the devices. (Or do something like a 13/8ths speed clock, which is 130MHz, distribute that and multiply it up. Again, the edges are aligned with the input clock, so it will work out.http://www.alteraforum.com/forum/showthread.php?t=1473&highlight=pll)