--- Quote Start ---
The output of the PLL is based on the input clock that feeds it, which comes from a pin(usually). So your Tco is from that input pin to the output pin. For example, if you had two compiles and one had a 1ns delay from the pin to the PLL, and the second one had a 5ns delay, the data's Tco would be considerably different. If you're in a situation where that delay "cancels out", i.e. you just care about a bunch of output pins related to each other, then it will cancel out when using the input pin too.
--- Quote End ---
The clock on the input pin runs at 80Mhz but the output of the pll runs at 260Mhz so a tco from the input clock to my output pins won't be valid, right?
Honored Contributor
