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Altera_Forum
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8 years ago

PLL Duty Cycle Issue

Hi All, I'm having an issue generating an output clock with any duty cycle other than 50%. The MegaWiz tool will accept the duty cycle and build the IP, but the resulting route fails during fittin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks for the reply sstrell,

I have looked at that section of the handbook. I was expecting the megawiz tool to flag a duty cycle that would result in an error. Or give me a duty cycle as close as it can. However, the fitter fails and reports the only legal value is 50%. So should set the parameters by hand to get the desired duty cycle? There is a check box to enable setting the physical parameters thru the megawiz tool. But it wasn't clear to me how to adjust duty cycle even with that.

I think I'm ok with this clock frequency driving directly to a pin from the pll, but I have the same results with 200 MHz output clock and a %55 duty cycle. My target device is 5AGXBA1D4F27C5

Thanks