PLL Duty Cycle Issue

From the Arria V device handbook. You don't mention what duty cycle you're trying (or if your target device is rated to even run at 600 MHz), but maybe this will help:

Programmable Duty Cycle

The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature

is supported on the PLL post-scale counters.

The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To

determine the duty cycle choices, the Intel Quartus Prime software uses the frequency input and the

required multiply or divide rate.

The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50%

divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for

duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the

counter driving the fbin pin to 50%.

Combining the programmable duty cycle with programmable phase shift allows the generation of precise

non-overlapping clocks.