Getting this hold timing error. Need help resolving it. PLL cross checking found inconsistent PLL clock settings: Clock: i_DAC_TOP|i_PLL|pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[...
No, you didn't have to break out the PLL output clocks like that. derive_pll_clocks is fine. I was referring to the 3 extra create_clock statements you have (sclk, clk_divider...). Those are coming from internal registers, not an input port of the device, so they should be in your .sdc as create_generated_clock commands, not create_clock.
As for the failing paths, those look like they are going to Signal Tap, which is debug logic that will be eventually removed. You don't really need to meet timing there.
FYI, you can't use create_clock to create internal clocks like that. You need to use create_generated_clock. I don't think that's related to the issue, though.
Is FPGA_CLK1 the input clock reference for the PLL? I presume it is based on the frequency, but the error is indicating that the wrong clock is being used as the reference input for the PLL.
FPGA_CLK1 clock is input to altcltctrl ip, then the output of altclkctrl is used in the PLL as the reference clock.
Would you still suggest to use create_generated_clock for FPGA_CLK1? I updated my sdc with these 4 lines using the derive_pll_clocks, let me know if this is correct:
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