PLL clock question

Right, I think I've worked out the source of my problems : badly written timing constraints. Probably the source of 90% of people's problems!

It also explains where that ...clk[0]~1 comes from.

Here's what I think was going on:

As mentioned at the start of this thread, there are 2 external clocks into this FPGA, an on board 40MHz clock and an off board 160MHz clock. The 40MHz is taken up to 160MHz internally by one PLL in the FPGA and the external 160MHz and internal 160MHz are both fed into a second PLL. The second PLL produces 160MHz (...clk[0]) and 40MHz (...clk[1]) out and is set up to default to use the external 160MHz source, but fail over to the internal 160MHz clock when the external 160MHz is not present. All the logic in the FPGA uses the two clocks out of the second PLL.

In my constraints file I had the statement "derive_pll_clocks" which was doing the correct thing and resulting in two sets of internal clocks out of the second PLL, one set being ...clk[0] and ...clk[1] referenced from the external 160MHz clock and the other set being ...clk[0]~1 and ...clk[1]~1 referenced from the internal 160MHz clock from the first PLL.

The problem I had was not properly excluded the timing path between these two sets, so Timing Quest was reporting on setup and hold between the two sets of clocks, even though only one set could be active at any one time.

I changed the constraints file to explicitly create the PLL derived clocks and then created correct clock groups to exclude checking timing between the two sets of clocks and everything works fine now.

The document found here really helped my understanding of what was going on and how to write constraints for derived clocks

http://www.alteraforum.com/forum/attachment.php?attachmentid=1166&d=1243964687 (http://www.alteraforum.com/forum/attachment.php?attachmentid=1166&d=1243964687)

Also thanks for your assistance Rysc in pointing me in the right direction!