PLL clock question

Thanks for that explanation on multi-cycle. I've read the TimeQuest User Guide but hadn't twigged that was the way to do it, I've made the change in my constraints file, curiously the timing has got worse by 1ns or so...

My design uses some LPM counters, which seem to both help and hinder. The timing improves when using them, but the timing violations reported all are inside the LPM auto-generated components and I'm not sure how I can fix that.

I'm still curious about the clock ending with ...clk[0]~1, is it the same global clock as the clock ending with ...clk[0] and is the clock skew reported the skew across the device on that global clock?