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Altera_Forum
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9 years ago

PLL and IO Setup/Hold

Hi, After compilation I am getting warning ID: 176441 which states: The I/O pin <name> cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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not sure exactly but my suspicion is that your requirement asks for clock skew while your pll mode is in normal compensating mode which deskews clock.

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That seems exactly right. Our design has an sdc file which specifies a max/min skew requirement.