PLL and Clock Control Block Fitting

Hi all,

Startix II GX:

I have the following problem. My design is using a reconfigurable PLL. I noticed, without external clock (inactive inclk0) it cannot be reconfigured. (I dont know why and I didnt find any corresponding topic. Im using intenal 10MHz scanclk. I tried using the areset with ISSP which is recommended in the errata sheet, but it didnt solved the problem, the scandone flag stays down). So, I would like to drive the PLL input (inclk0) with an internal 10MHz during the reconfiguration and after when the reconfiguration is done I would switch to the external clk. The problem is that I cannot use the PLL's switchover circuit, cos I need to use an input which is not corresponds to an enchanced PLL. (the clk input is in a wrong side of the FPGA, and there are no enhanced plls only fast plls.) So that I would use a clock control block to multiplex the clock lines. It means that the clock control block multiplexer has two inputs, one from an other pll and one from a global clock line (from an other clock control block probably). The output of the mux goes to the input of the reconfigurable PLL. Finally I passed the design assistant with connecting the proper inputs of the clock control block. But the fitter cannot fit this design with the following errors:

Error (164015): Can't place fast or enhanced PLL "...altpll:altpll_component|pll" in target device due to device constraints

Error (176378): Can't place node ...altpll:altpll_component|pll at PLL_1 because it potentially conflicts with the location constraints of Clock Control Block ...altclkctrl:clockmux2_inst|altclkctrl_mls:auto_generated|clkctrl1 and its inclk sources

Error (176379): Clock Control Block ...altclkctrl:clockmux2_inst|altclkctrl_mls:auto_generated|clkctrl1 has location constraint <nothing>

Error (176381): Source of inclk[2] is node ...pll_reconfig:pll_reconfig_inst|altpll:altpll_component|_clk0 with location constraints PLL_12

Error (176381): Source of inclk[3] is node ...|altpll:altpll_component|_clk1 with location constraints <nothing>

Error (176378): Can't place node ...altpll:altpll_component|pll at PLL_5 because it potentially conflicts with the location constraints of Clock Control Block ...altclkctrl:clockmux1_inst|altclkctrl_mls:auto_generated|clkctrl1 and its inclk sources

Error (176381): Source of inclk[1] is node external_clk_i with location constraints PIN V37

Error (176381): Source of inclk[3] is node ...altpll:altpll_component|_clk1 with location constraints <nothing>

Error (176387): Can't place ...altpll:altpll_component|pll at location PLL_7 because it uses a Clock Control Block with dynamic clock select

Error (164019): Can't place fast or enhanced PLL "...altpll:altpll_component|pll" in PLL location PLL_12 because location is already occupied by node "...pll_reconfig:pll_reconfig_inst|altpll:altpll_component|pll"

Am I going on the rigth way to do a certain reconfiguration? (The proper function would be: even if there is no clock, the pll reconfiguration should be managed, and after it cant lock, but the reconfiguration is done.) Or the pll should be reconfigured even with inactive inclk0?

Thank you for your help!