Please send me in the correct direction.

I have a 4 bit vector as an input, i must split this into two 2 bit vectors (symbols) .For each symbol I need to send to the output the 8 values which are stored in arrays. I am new to VHDL so any advice on improvement to my code is welcomed.

This is what I have done so far

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

entity mod2 is

Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0);

reset : in STD_LOGIC;

clock2 : in STD_LOGIC;

data_out : out STD_LOGIC_VECTOR (7 downto 0));

end mod2;

architecture Behavioral of mod2 is

signal symbol : std_logic_vector (1 downto 0);

--signal symbol2 : std_logic_vector (1 downto 0);

signal a : integer range 0 to 7 :=0;

signal b : integer range 0 to 7 :=0;

signal c : integer range 0 to 7 :=0;

signal d : integer range 0 to 7 :=0;

signal count : integer range 0 to 16 :=0;

signal data_out_a : integer range -128 to 127;

signal data_out_b : integer range -128 to 127;

signal data_out_c : integer range -128 to 127;

signal data_out_d : integer range -128 to 127;

type a_array is array (0 to 7) of integer range -128 to 127; -- symbol 00

signal a_look_up : a_array := (0, 32, 64, 32, 0, -32, -64, -32);

type b_array is array (0 to 7) of integer range -128 to 127; -- symbo1 01

signal b_look_up : b_array := (0, 64, 127, 64, 0, -64, -128, -64);

type c_array is array (0 to 7) of integer range -128 to 127; -- symbol 10

signal c_look_up : c_array := (0, -32, -64, -32, 0, 32, 64, 32);

type d_array is array (0 to 7) of integer range -128 to 127; -- symbol 11

signal d_look_up : d_array := (0, -64, -128, -64, 0, 64, 127, 64);

begin

process(clock2, reset)

begin

if reset = '1' then

count <= 0; --set counter

elsif clock2='1' and clock2'event then

if count <= 15 then -- check for max value

count <= count + 1; --increment

else

count <= 0; -- roll over

if count < 8 then symbol <= data_in(3 downto 2);

else symbol <= data_in(3 downto 2);

end if;

end if;

end if;

--end process;

case symbol is

when "00" => data_out <= std_logic_vector (to_signed(data_out_a, 8));

data_out_a <= a_look_up(a);a <= a + 1;

when"01" => data_out <= std_logic_vector (to_signed(data_out_b, 8));

data_out_b <= b_look_up(b);b <= b + 1;

when"10" => data_out <= std_logic_vector (to_signed(data_out_c, 8));

data_out_c <= c_look_up(c);c <= c + 1;

when"11" => data_out <= std_logic_vector (to_signed(data_out_d, 8));

data_out_d <= d_look_up(d);d <= d + 1;

when others => null;

end case;

end process;

end Behavioral;