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Altera_Forum's avatar
Altera_Forum
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13 years ago

Please send me in the correct direction.

I have a 4 bit vector as an input, i must split this into two 2 bit vectors (symbols) .For each symbol I need to send to the output the 8 values which are stored in arrays. I am new to VHDL so any ad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

yes, thats the sensitivity list.

If you want the case statement to be synchronous, put it inside the if rising_edge(clk) part of the code.