Forum Discussion
New ContributorPlatform Designer Nios HDL generation
If you look into the project directory -> ip -> {example_ip_name} -> synth folder, that's where the top level vhdl file generated for that particular IP, used in your qsys system.
example file path: .../<project directory>/ip/<example_ip_name>/synth
You can find it at the top level qsys synth folder as well, go to project directory -> {top_qsys_name} -> synth.
example file path: .../<project directory>/<top_qsys>/synth
The other generated file with sub-system component are usually generated in .v or .sv files format.
example file path with sub-system/ip:
.../<project directory>/ip/<example_ip_name>/<sub-system>/synth
.../<project directory>/<top_qsys>/<example_ip_name>/synth
Best Regards,
Richard Tan
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Frequent ContributorHi,
Greetings and welcome to Intel's forum.
Yes correct, the generated files are in .v format after you generate HDL for your simulation files.
The difference between a .v and .vhd file is <your_system>.v and <your_ip>.vhd
Here is the list of generated files from Quartus Platform Designer for your reference: https://www.intel.com/content/www/us/en/docs/programmable/683609/22-3/files-generated-for-systems.html
Hope this clarifies your doubts.
Thank you.
Regards,
Kelly Jialin, GOH
New ContributorHi @KellyJialin_Goh I am getting .v and .sv file for synthesis hdl. I didn't select simulation option. Though I have selected "VHDL" in HDL file option, It is generating .v/.sv([folder same name as Qsys project]->synthesis->submodules).
Please let me know, If I missing something
Thanks,
Subhabrata
