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Subhabrata's avatar
Subhabrata
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Platform Designer Nios HDL generation

I have created NIOS II based system in Platform Designer (Quartus Prime Lite 18.1). completed all connection, memory mapping and IRQ. But to generate HDL (Generate -> generate HDL), I am getting on...
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  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    If you look into the project directory -> ip -> {example_ip_name} -> synth folder, that's where the top level vhdl file generated for that particular IP, used in your qsys system.

    example file path: .../<project directory>/ip/<example_ip_name>/synth

    You can find it at the top level qsys synth folder as well, go to project directory -> {top_qsys_name} -> synth.

    example file path: .../<project directory>/<top_qsys>/synth


    The other generated file with sub-system component are usually generated in .v or .sv files format.

    example file path with sub-system/ip:

    .../<project directory>/ip/<example_ip_name>/<sub-system>/synth

    .../<project directory>/<top_qsys>/<example_ip_name>/synth


    Best Regards,

    Richard Tan

    p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.


KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi,

Greetings and welcome to Intel's forum.


Yes correct, the generated files are in .v format after you generate HDL for your simulation files.

The difference between a .v and .vhd file is <your_system>.v and <your_ip>.vhd


Here is the list of generated files from Quartus Platform Designer for your reference: https://www.intel.com/content/www/us/en/docs/programmable/683609/22-3/files-generated-for-systems.html


Hope this clarifies your doubts.

Thank you.


Regards,

Kelly Jialin, GOH


Subhabrata's avatar
Subhabrata
Icon for New Contributor rankNew Contributor
2 years ago

Hi @KellyJialin_Goh I am getting .v and .sv file for synthesis hdl. I didn't select simulation option. Though I have selected "VHDL" in HDL file option, It is generating .v/.sv([folder same name as Qsys project]->synthesis->submodules).

Please let me know, If I missing something

Thanks,

Subhabrata