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Gauthier_Auvray's avatar
Gauthier_Auvray
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3 years ago

platform designer generation

Hi, I would like to use the "generate tcl file for project" feature to be able to re-create and build a project on a CI system (the design uses Platform Designer). 1. I can generate the TCL file of...
Hdl
Platform
Gauthier_Auvray's avatar
Gauthier_Auvray
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3 years ago

OK thanks! I will use explicit component declaration to instantiate verilog in VHDL file.