Forum Discussion
MMavi
New Contributor
7 years agoPlatform designer generates faulty interconnect addressing unless I use Assign Base Addresses. I don't want to use it since Addresses changes for every change in the design.
Hi, I use Quartus Prime 17.1 Standard Edition. Currently, I work on a project with arria10SoC FPGA. In the project, I use Platform designer to connect some custom blocks to HPS via LWB. There are ...
MMavi
New Contributor
7 years agoHi,
I solved the problem it was the network address depth of Avalon MM Slave Translator that I used. It was at the default value and I didn't see it for a while. It was larger than the needed address depth and it confused the platform designer somehow.
When I correct it, the problem solved.
Thanks anyway for replying.