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Aswinkrishnan's avatar
Aswinkrishnan
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer Avalon Communication

Hi I am trying to generate a simple system which consists of an Avalon MM master BFM and an Avalon memory mapped slave. My avalon slave consists of two components, having an interface to the other ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

In Platform Designer, you'll able to see the output signals of Avalon Memory Mapped Slave BFM after show signals. After HDL generation, those ports also available in the .v file check the images below.

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.