Occasional Contributor
Super Contributor1) Not sure what you mean here. "Doesn't create ports"? If you're creating a custom component (using Component Editor I presume) you create the ports and specify their function on the Signals & Interfaces tab. Maybe more detail is needed here.
2) From the Generate menu, you should choose to generate a testbench system design for your custom component. This will automatically configure and attach an appropriate BFM to it and create the simulation scripts you would use, but you have to write the testbench using the BFM API to control the commands sent (and monitor the responses back). This training is a little old, but it covers the basics: https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true
Occasional ContributorMy master has the clock and reset as input ports. The output ports should be avalon slave address and etc. But the AVS ports are not visible in the ports of the HDL generated.
