Platform designer automatic interconnect bandwidth behavior

We are aware of the fact that width is converted automatically; what we do not know, is whether the interconnect locks the slave device for the entire duration of the master device transfer or the slave is locked only for the time necessary for the transfer of data at slave interface? In other words, does the burst transaction at the fast slave interface take the same amount of time as the transaction on the slow master interface? There are some QSYS settings (Per-burst-type converter, Platform Designer Guide, 3.1.9.1. Burst Adapter Implementation Options) looking relevant to this situation, could you please explain the usability of these on our scenario as well?

BCT_Intel: Your answer does not make much sense to us, could you please elaborate? Connecting a 64-bit master to a 512-bit (internal) width DDR will likely not result in only 8 DQ signals toggling(?)

F.