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FRoth's avatar
FRoth
Icon for New Contributor rankNew Contributor
7 years ago

Platform designer automatic interconnect bandwidth behavior

We have a DDR3 memory with internal interface width 512 bits running at 200 MHz Avalon bus speed. We want to connect several master components to this memory using the one Avalon slave port. We are u...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Sir,

For the data width, you have to use full 512bits to fully utilize the bandwidth. The interconnect will not help to expand the data width to adapt memory local interface data width.

This mean if you use 64bits, you only use 1/8 of the memory from the DDR3 device. I believe the interface data width is 64 bits. So, if you running the simulation, you will only see 8 bits of the DQ is working.