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RWitt's avatar
RWitt
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7 years ago

Platform Designer - A10 PCIe SR-IOV core set for (3) PFs - do the PFs have to share the 64 extended non-posted tags, or does each PF get 64 tags?

I'm trying to give each PF as many tags as possible, but are they limited to the hard-core's max support of 64 "total" (not per PF?)? I've got a different question that asks about moving the tag sup...
RWitt's avatar
RWitt
Icon for New Contributor rankNew Contributor
7 years ago

As mentioned in the other thread. 64-tags for 100Gbps designs is not acceptable. Intel needs to provide the tag support in the hard-core or allow that tag management to be done in the Application Layer. The MM-DMA core that supports 256-tags is not an option for us, and I am sure it is not for others as well.

Please escalate a request to engineering to add support for 256-tags, ASAP - for the ST core and ST-SR-IOV.

Regards,

Bob