Platform Designer - A10 PCIe core - with SR-IOV not enabled and MSI-X enabled I can't export the msix signals.

When you open an Arria10 project in Quartus Prime Pro, Tools-> Platform Designer, you have your qsys with (in our case) a qsub_pcie_inst, drill into that and you can modify the parameters of the pcie_a10_hip_inst. For System Settings (Parameters main tab) you can select the Application interface type: "Avalon-ST" or "Avalon-ST with SR-IOV" (only two choices in PD). If you select Avalon-ST, on the "PCI Express/PCI Cabilities" tab you select "Implement MSI-X", which enables it, and then you select its settings, then you save and Generate HDL. The generated RTL's int_msi Conduit does not contain the MSI-X signals (app_msix_req/ack/etc). If I had chosen the "Avalon-ST with SR-IOV" "Application interface type" under "System Settings" and did the same (with different tabs) the app_msix_... signals are exposed to the application layer. I'll try to show the two in images, assuming that is what you mean by "snapshots of the IP"(?). Note that the generated top-level(s) either have the msix signals or not depending on the above settings.

Update: 12/04/18 - I was looking at the MM-DMA link you gave me; with an Avalon-MM DMA environment selected the MSI-X signals appear at the application layer (when enabled), along with additional control signals I can see in an errata but not in the manual's signal list (such as msix_control[15:0]).