Platform Design tool gets error when generating system: Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga_lite/19.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt"

I have exactly the same issue and have tried both your your above suggestions without luck. I am trying to generate the GHRD for the DE-10 Nano (unchanged) and had it fail on Quartus 18.1 lite. I assumed it was a conversion error (as the GHRD (since it was made with 16.0. Tried it with 17.1 lite, 16.1 lite and 16.0 lite and all had the same issue. Contacted Terasci supported and they said they generated using standard not lite. Installed a trial of 16.0 Standard, same issue. Terasic now suggests trying a different computer or reinstalling the O/S =(.

Here is a dump of the generation report if it helps...

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[I trimmed the working part so the post would be small enough]

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Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/altera/16.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Execution of command "{C:/altera/16.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed

Error: border: Error during execution of script generate_hps_sdram.tcl: seq: ]2;Altera Nios II EDS 16.0 [gcc4]

Error: border: Error during execution of script generate_hps_sdram.tcl: seq: child process exited abnormally

Error: border: Error during execution of script generate_hps_sdram.tcl: seq: add_fileset_file: No such file C:/Users/mattpaul/AppData/Local/Temp/alt8423_4643917322721710918.dir/0003_seq_gen/hps_AC_ROM.hex

Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining

Error: border: Execution of script generate_hps_sdram.tcl failed

Error: border: 2020.06.10.10:47:25 Info:

Error: border: ********************************************************************************************************************

Error: border:

Error: border: Use qsys-generate for a simpler command-line interface for generating IP.

Error: border:

Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.

Error: border:

Error: border: ********************************************************************************************************************

Error: border: 2020.06.10.10:47:29 Warning: Ignored parameter assignment device=5CSEBA6U23I7

Error: border: 2020.06.10.10:47:29 Warning: Ignored parameter assignment extended_family_support=true

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.seq: This module has no ports or interfaces

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit.

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit.

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit.

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit.

Error: border: 2020.06.10.10:47:33 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master

Error: border: 2020.06.10.10:47:33 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH

Error: border: 2020.06.10.10:47:35 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll"

Error: border: 2020.06.10.10:47:35 Info: p0: Generating clock pair generator

Error: border: 2020.06.10.10:47:36 Info: p0: Generating hps_sdram_p0_altdqdqs

Error: border: 2020.06.10.10:47:42 Info: p0:

Error: border: 2020.06.10.10:47:42 Info: p0: *****************************

Error: border: 2020.06.10.10:47:42 Info: p0:

Error: border: 2020.06.10.10:47:42 Info: p0: Remember to run the hps_sdram_p0_pin_assignments.tcl

Error: border: 2020.06.10.10:47:42 Info: p0: script after running Synthesis and before Fitting.

Error: border: 2020.06.10.10:47:42 Info: p0:

Error: border: 2020.06.10.10:47:42 Info: p0: *****************************

Error: border: 2020.06.10.10:47:42 Info: p0:

Error: border: 2020.06.10.10:47:42 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"

Error: border: 2020.06.10.10:47:43 Error: seq: Error during execution of "{C:/altera/16.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally

Error: border: 2020.06.10.10:47:43 Error: seq: Execution of command "{C:/altera/16.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed

Error: border: 2020.06.10.10:47:43 Error: seq: ]2;Altera Nios II EDS 16.0 [gcc4]

Error: border: 2020.06.10.10:47:43 Error: seq: child process exited abnormally

Error: border: 2020.06.10.10:47:43 Error: seq: add_fileset_file: No such file C:/Users/mattpaul/AppData/Local/Temp/alt8423_4643917322721710918.dir/0003_seq_gen/hps_AC_ROM.hex

Error: border: while executing

Error: border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $file_pathname"

Error: border: ("foreach" body line 4)

Error: border: invoked from within

Error: border: "foreach file_pathname $return_files_sw {

Error: border: _dprint 1 "Preparing to add $file_pathname"

Error: border: set file_name [file tail $file_pathname]

Error: border: add_fileset_file $..."

Error: border: (procedure "generate_sw" line 18)

Error: border: invoked from within

Error: border: "generate_sw $name $fileset"

Error: border: ("if" then script line 4)

Error: border: invoked from within

Error: border: "if {[string compare -nocase $fileset QUARTUS_SYNTH] == 0} {

Error: border: set top_level_file "altera_mem_if_hhp_qseq_synth_top.v"

Error: border: add_fileset_file $top_level_fi..."

Error: border: (procedure "generate_files" line 4)

Error: border: invoked from within

Error: border: "generate_files $name QUARTUS_SYNTH"

Error: border: (procedure "generate_synth" line 3)

Error: border: invoked from within

Error: border: "generate_synth altera_mem_if_hhp_qseq_synth_top"

Error: border: 2020.06.10.10:47:43 Info: seq: "hps_sdram" instantiated altera_mem_if_hhp_ddr3_qseq "seq"

Error: border: 2020.06.10.10:47:43 Error: Generation stopped, 3 or more modules remaining

Error: border: 2020.06.10.10:47:43 Info: hps_sdram: Done "hps_sdram" with 7 modules, 33 files

Info: border: "hps_io" instantiated altera_interface_generator "border"

Error: Generation stopped, 2 or more modules remaining

Info: soc_system: Done "soc_system" with 65 modules, 123 files

Error: qsys-generate failed with exit code 1: 68 Errors, 4 Warnings

Info: Finished: Create HDL design files for synthesis