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Altera_Forum
Honored Contributor
14 years agoThanks for your reply.
I am proposing an analytic power model for Network switch components in FPGA, I need to estimate the power consumed in some wires connecting the components by PowerPlay Analyzer. In my design, I need to fix the place of each components and interconnection wires too. How can I create design out of LUTs and then logic lock them all?