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dmanikanth's avatar
dmanikanth
Icon for New Contributor rankNew Contributor
3 years ago

Pipelining output data of RAM (M20K) through Quartus tcl console

Hi I want to pipeline output data of M20K RAM block as few M20K --> M20K paths which are not meeting timing by around 2ns. I have tried ECC pipelining but getting error that the RAM should be of 5...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Which RAM IP that you are using in your platform designer? Perhaps you can share a simple project .qar file so I can understand better.

Some ways that I can think of is to add register at the RAM block output and change the project setting so that Quartus is allowed to RAM retiming. (change this in the Fitter Advanced setting)

You may try to change the Optimization Mode to "High Performance Effort".


Best Regards,

Richard Tan


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