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dmanikanth's avatar
dmanikanth
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3 years ago

Pipelining output data of RAM (M20K) through Quartus tcl console

Hi I want to pipeline output data of M20K RAM block as few M20K --> M20K paths which are not meeting timing by around 2ns. I have tried ECC pipelining but getting error that the RAM should be of 5...
dmanikanth's avatar
dmanikanth
Icon for New Contributor rankNew Contributor
3 years ago

Hi

I am using Agilex Agfa022 device and the RAM i am having is an auto generated altsynram inside sgbm block. Some I am unable to edit the RAM ip in the platform designer where i was able to go till 1 level into sgbm block.

I have also run Fast Forward timing closure recommendation, where i have got fully registering the RAM's as one of the suggestions. Not sure how to apply the tool recommendations in the RTL as platform designer is not helping to navigate to RAM ip inside sgbm block.