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dmanikanth's avatar
dmanikanth
Icon for New Contributor rankNew Contributor
3 years ago

Pipelining output data of RAM (M20K) through Quartus tcl console

Hi I want to pipeline output data of M20K RAM block as few M20K --> M20K paths which are not meeting timing by around 2ns. I have tried ECC pipelining but getting error that the RAM should be of 5...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Which device are you using? Are you using the RAM Intel IP?

In the Intel IP, there is an option with "Which ports should be registered?" . Tick the " 'q' output port" option should add pipeline register at the output.

Is this what you want to meet the design timing?


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.