Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Pipelined Datapath Custom Instructions

I've been looking for a while to find some information and tutorials on how to run pipelined custom instructions.

Let's say we have (A+B) * (C+D) and we have 10 values for each of A,B,C,D, so 40 values total. How can I write VHDL for doing this using multicycled costum instructions at it's most optimized and lpms. This is using a simple computer built with SOPC (nios 2, on chip mem, jtag, etc...). I created a model with an FSM that does it with two cycles as described below.

The most confusing part for me is how to write the c program in NIOS IDE for it. I understand how to do:

- load A[0] and B[0] {using CI(n=0) }

- load C[0] and D[0] and at same time do A[0] + B[0] {using CI(n=1)}

- load A[1] and B[1] and get result of the (A[0] + B[0]) * (C[0] + D[0]) {again using CI(n=0) }

....

but you can optimize it further by loading A[1] and B[1] during the C[0] + D[0] operation, doesn't have to wait for the whole operation to finish.

How is that done, as is it possible? Where can i find some info on this.

Thank you

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You want a pipelined circuit?

    If yes just inert pipeline registers and arithmetic block the way you need them.

    On an FPGA, however, you can execute the whole operation in one clock cycle since you have pleny of adder and multpliers implemented.

    The problem can be if you have to access to the external memory in order to load A,B,C,D data.