New Contributor
New ContributorHi FvM,
thanks for your replay and the Infos. I'm testing my design on the Cyclone IV FPGA first for other FPGA so i think you're right about expecting too much form it.
I have to use set_mulicycle_path for the outputs otherwise i'll have setup and hold violations. Is there something else i can do there ?
- set_multicycle_path -setup -end -from [get_registers {wr_fifo:DUT10|q_wurzel_s*}] -to [get_ports {q*}] 2
- set_multicycle_path -hold -end -from [get_registers {wr_fifo:DUT10|q_wurzel_s*}] -to [get_ports {q*}] 1
I tried yesterday what the report timing closure recommendations in Timing Analyzer and it showed me this:
- turn off auto shift register replacement in Analysis & synthesis settings.
- turn on physical synthesis for combinational logic in fitter Setting.
Surprisingly it worked and now im having f_max in worst-case up to 257.4 MHz.
Is it right to change the setting like that or what ?
thanks in advance
Super ContributorNew ContributorHi FvM,
thanks for your relpy.
Your were right about the lpm_divide speed, i tried the PLL with 4 different outputs-Freqence (100MHz, 150MHz, 200MHz and 300MHz) and im getting these timing errors for lpm_divide only when im using the 300MHz clock, max frequency it can do 220MHz with these same parameters.
But now im getting removal timing errors, i didn't get this before and don't know why im getting these now
Please refer to the .zip file for its contents:
- RTL Viewer
- Timing summary
- Removal 'reset' report
- .sdc file
PS: i got this now. it should be contacted (assignment) to the 'reset' pin hardware.
please take a look in zip-file.
thanks in advance
