Forum Discussion

amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago
Solved

Pipeline Factor in SignalTap

Hello, In SignalTap there is an option to add the Pipeline to the signals. Should the pipeline acts as synchronizers? Will the set_false_path constraints be added automatically? Thanks!
  • FvM's avatar
    FvM
    3 years ago

    Hello,

    Debug Tools User Guide explains:

    "The Pipeline factor setting indicates the number of pipeline registers that the Intel
    Quartus Prime software can add to boost the fMAX of the Signal Tap Logic Analyzer."

    https://cdrdv2.intel.com/v1/dl/getContent/667125?fileName=ug-qps-debug-683552-667125.pdf

    Not related to synchronizers. There's no specific feature to support the consistent capture of asynchronous signals. Signaltap operation is described so:

    "Synchronous sampling of data nodes using the same clock tree driving the logic under test."

    Regards

    Frank

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Do you find the clarification above helpful?

Let me know if you have any further concern or consideration.


Best Regards,

Sheng


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago

How can adding the pipeline registers increase the fMAX? Should re-timing be applied to these registers? How?