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Altera_Forum
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14 years ago

Pin Plannung for DDR2 SDRAM

Hello everyone,

I would like to connect two DDR2 SDRAM memories to a Cyclone III FPGA.

Each memory has 16 Data Bits, SSTL_18 Standard and 512 MBit.

In order to save pins on the FPGA, I would like to connect the RAMs to only two High Speed Banks. During Pin Planning, I realized, that there aren't enough Pins. Only 5 Pins are remaining. This is annoying, because so I need one more Bank for only 5 Pins.

I tried to connect some cotrol Signals to the Vref Pins, because they can be used as IO Pins, if not necessary for voltage supply. But Live IO Check says, that the Vref Pins are needed for 1,8 V supply.

Is it possible to use the Vccio Pins for 1,8 V Reference and the Vref Pins for DDR2 control signals?

Thanks in advance!

Christopher

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The Vref pins in the banks with the DQ signals need to be connected to the midpoint of the 1.8V supply voltage to the SDRAMS, or 0.9V Usually this 0.9V is either derived from the Vtt controller when using DIMMs or made with a 1k/1k resistor divider in the case of single chips.

    Also if you drive too many outputs and bidirs in a single IO bank the compiler will also complain. I estimate you will need 4 banks of a 256 BGA or 3 of a 484 BGA device. I'm not sure about the 324 BGA one.

    Live IO-check is not complete either, it will only check the number and type of IOs. You may want to instantiate a DDR2 controller together with the Altera-provided test driver to verify proper connection of DQ, DQS and DM pins.