Pin Planner - by board wire?

Hi Martin,

Eventually you will find that you do not use the GUI, eg. if you are rebuilding a project, you just want to do "one thing". In my case, that one thing is to run a synthesis script.

Given that the pin assignments and functions on a board, such as your evaluation board never change, I find it more convenient to define a top-level entity description with the pins named per the board design (or slightly modified if I don't like the names used on the schematic). I then create a pin assignments Tcl script to create the pin assignments in the .qsf file.

A design that targets a specific evaluation board is then wired into the top-level entity. For example, lets take the BeMicro board with a Cyclone III FPGA and the BeMicro-SDK board with a Cyclone IV, here's a couple of layers of my hierarchy;

boards/bemicro/cyclone3/share/scripts/pinout.tcl  Pin assignments script
boards/bemicro/cyclone3/basic/src/bemicro.vhd    "Basic" top-level design
boards/bemicro/cyclone3/basic/scripts/synth.tcl  Synthesis script
boards/bemicro/cyclone3/avalon/src/bemicro.vhd    "Avalon" top-level design
boards/bemicro/cyclone3/avalon/test/bemicro.vhd   Testbench
boards/bemicro/cyclone3/avalon/scripts/synth.tcl  Synthesis script
boards/bemicro/cyclone3/avalon/scripts/sim.tcl    Simulation script
  
boards/bemicro_sdk/cyclone4/share/scripts/constraints.tcl  Pin assignments and constraints script
boards/bemicro_sdk/cyclone4/basic/src/bemicro.vhd    "Basic" top-level design
boards/bemicro_sdk/cyclone4/basic/scripts/synth.tcl  Synthesis script

Every board is created with a "basic" design. That design just blinks an LED, or wires a push-button to an LED, something "basic" :) But more importantly, it drives every output or bidirectional output with a sane value; usually to a deasserted value, or asserted if its a reset control to say an external PHY. This ensures that everything on the board is put into a sane state, no matter what.

I can then copy-and-paste that reference design as the top-level design for any new designs. Again, any unused interfaces get left at their sane defaults.

If you want example code/scripts, let me know, and I'll post it.

What development board do you have?

Cheers,

Dave

In general, you use the Pin Planner because you want to layout out your pins in specific locations because you're going to spind a board. So you know the flash will be placed in a specific location compared to the device, the data and address will go in a specific order, and so you place your pins that way.

Your addressing the problem where the board is already laid out, you just want to make sure your RTL I/O match the correct connectsions on the board. As mentioned, Tcl is probably the best way to do that. Just creating some variables to hold the translation:

set switch_5 PIN_A3

Then if you want my_input[5] on it, do:

set_location_assignment $switch_5 -to {my_input[5]}

You could then just source the Tcl file, or add it as a pre-flow script.

(Another option is to have a top-level RTL shell that has the correct port names and pin assignments. You would just use that to instantiate your HDL underneath, and hook my_input[5] of your code to the top-level port switch_5.)

Of course, this isn't very useful for a specific person since they would usually only do it once or twice. It could be useful if a lot of people use it, which I believe is your goal, but distribution like that is often difficult. Good luck.

I decided to write the tool...

The tool is not tested nor documentend, yet, but I hope it works and I and other users of evaluation boards will like it!

See screenshot attached.