New Contributor
Frequent ContributorHi ,
Can you verify that the options which is provided in the IP is correct and similar to the one given in the older Quartus version before the IP update. You can also have a look at the below article.
https://www.intel.com/content/www/us/en/support/programmable/articles/000076453.html
Thanks and Regards
Anil
New ContributorHi,
The link you provided talks about the mem_alert_n pin however as you can see from the error message I posted I am having issues with the reference clock input pin of the EMIF IP.
The EMIF is part of a bigger platform designer system within our design.
I am not sure how to determine exactly what you are asking, however attached are the EMIF *.ip files from before and after the IP upgrade in the new tool (before_emif.ip is the ip file from the older 18.0.1 quartus version and after_emif.ip is from the 2021.2 quartus tool after having done the auto ip upgrade).
Can you tell from this if there is an issue? I am still trying to run the design in the new tool but can't because of the error I am getting.
Thanks!
