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AThom47's avatar
AThom47
Icon for New Contributor rankNew Contributor
4 years ago

pin placement error after upgrade from 18.0 pro to 21.2 pro

Hi, I have an Arria10 design that compiles fine in quartus 18.0 pro but throws the following error after upgrading to quartus 21.2 pro: "Error (175020): The Fitter cannot place logic pin in regio...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

You shouldn't need an .ini file for Quartus unless you are enabling beta or other non-standard features.

Did you upgrade all the IP through regeneration of your Platform Designer system, including the HPS? Check to make sure that all your IP (Platform Designer and otherwise) are up to the latest version.

  • AThom47's avatar
    AThom47
    Icon for New Contributor rankNew Contributor
    4 years ago

    Yes, I have updated all IPs through the auto upgrade process with no errors, the versions are all updated from 18.0 to a mix of 19.1, 19.1.0 , 19.2.0, 19.2.2, 19.3.1 and 20.0.0

    However I am still getting the following error:

    Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Error (175020): The Fitter cannot place logic pin in region (78, 142) to (78, 143), to which it is constrained, because there are no valid locations in the region for logic of this type.
    Info (14596): Information about the failing component(s):
    Info (175028): The pin name(s): EMIF_REF_CLK
    Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
    Error (175005): Could not find a location with: HPS_IOPLL_REFCLK_PIN (1 location affected)
    Info (175029): AL27
    Info (175015): The I/O pad EMIF_REF_CLK is constrained to the location PIN_AL27 due to: User Location Constraints (PIN_AL27) File: C:/xyz/source/xyz/xyz.vhd Line: 113
    Info (14709): The constrained I/O pad is contained within this pin
    Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.
    Error (16297): An error has occurred while trying to initialize the plan stage.

    As mentioned above I found other people having the same issue but in different quartus versions. I tried their solutions but they did not help. For reference the other posts about this that I found are here:

    https://community.intel.com/t5/Intel-Quartus-Prime-Software/Fitter-Error-with-Quartus-19-4-and-not-Quartus-19-1-for-HPS/m-p/595633/highlight/true

    and

    https://community.intel.com/t5/Programmable-Devices/clk-pll-input-location-for-DDR4-HPS-arria10sx066f34I2SG/m-p/728838

    Any help on how I can fix the issue so I can build with quartus 21.2 is appreciated.

    Thanks!