PIN Mapping Issue

Hello Friends,

I am a starter in FPGAs and learning for starting a project of implementing a communication protocol in Cyclone V. I have the Deo-Nano-Soc development board from Terasic. Ok my question is , I tried to do a project from the tutorials of the board and I was able to successfully synthesize and elaborate the project. I have attached the snapshot of the project with this post. Its below.

http://www.alteraforum.com/forum/attachment.php?attachmentid=11008&stc=1

When I do Assignements -> Pin Planner , some of the Input and Output ports are not coming in the PIN mapper.

CLOCK_50    Input    PIN_V11    3B    B3B_N0    2.5 V (default)        12mA (default)    
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
counter_out    Output                2.5 V (default)        12mA (default)    1 (default)
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It is coming as above, but the input pins KEY[0], kEY[1] and the output pins LED[3..0] is not coming in the above list. But CLOCK_50 and orthogonal buses are visible. I can share more details if required.

Does anyone faced this problem? .Any help would be greatly appreciated.

Thanks,

Kannoth