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Altera_Forum's avatar
Altera_Forum
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10 years ago

PID in vhdl

hai all,

I am trying to simulate a PID controller in VHDL... I have tried a code but I am getting output only every two clock cycles!!! I have attached the vhdl code and its corresponding test bench.... Can anyone help me regarding this issue. Thanks in advance.... :-)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hi,

    uh, better respond late than never I guess :cool: the signal "output", which is used also used as an input, is not initialized. If you run this through ModelSim, it will immediately tell you that it will return all X's as a result of an arithmetic operation with that.

    Either define your port as "output: buffer std_logic_vector(15 downto 0) := (others => '0')" or introduce a reset signal.

    Best regards,

    GooGooCluster