PI loop filter logic in Verilog

You should not follow that paper as it seems to me it is out of date and the author doesn't seem to know that you can use signed values instead of "pdup" logic. He assumed magnitude then applying for difference sense in logic.

For proper PLL you need to design a frequency generator inside your rtl. Then input another close frequency that you can vary its frequency or phase slightly. You compare the two frequencies (input and reference) and you may add dividers as well if you want more advanced PLL. The comparator will output the signed value of difference which you take to the integral and accumulator directly without the logic proposed in that paper. Then apply filtered output on the input frequency phase.