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Altera_Forum
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8 years ago

PI loop filter logic in Verilog

Hello, the attached photo with the verilog code is taken from the attached article. There are two variables, integral and proportional when clk=1 thenintegral decreases ,when clk=0 then it decreas...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Your input is the phase error (either + or -)

The PI filter is just an accumultor of this error : accum <= accum + error (the result can lso be divided as a fraction=leaky accumulator)

The Proportional term is just part of error sample added to accum, How much P is added is up to testing

Note that you are mistaken about clock edge. The error is either + or - tested on same clock edge