Phase shift for the read DQS pin must be set to 72 or 90 instead of 67

Hi,

I'm getting the following critical warnings and can't figure out how to solve them :

Critical Warning: Phase shift for the read DQS pin, FPGA_LDQS_R, must be set to 72 or 90 instead of 67

Critical Warning: Phase shift for the read DQS pin, FPGA_UDQS_R, must be set to 72 or 90 instead of 67

I couldn't either find any document describing them.

Has anyone already encountered this warning before ?

I'm using Quartus 9.0, a Stratix-III and the SDRAM interface is "DDR SDRAM High Performance Controller".

Thanks,

P9