PCIe hard IP BAR to On-chip memory addressing

Hi,

From your design, I observed that you are not using the correct clock on the on chip memory. The clock should be from the PCIe Clock output so that the clock is sync between Bar 0 and On Chip Memory.

Please refer to https://fpgacloud.intel.com/devstore/platform/14.0.0/Standard/an-456-pci-express-high-performance-reference-design-for-cyclone-iv-gx-fpga/ for the design example.