Forum Discussion
SivaKona
Occasional Contributor
Occasional Contributorpcie gen3x8 DMA EndPoint with HPTXS path is not meeting timing
Hi , I have generated an FPGA model with PCIe DMA EP and onchip Memory as shown in the attached "DMA_EP_OnchipMem_model.png" file. I have instantiated an Onchip Memory of size 16MB. Seeing Setup...
You may try to lower your clock frequency, with increased in clock period, it is easier to meet setup.
Or you can add pipeline stages. You may checkout the video below
https://www.youtube.com/watch?v=g6SjVhVderc
RichardT_altera
Super Contributor
Super ContributorI’m glad that your question has been addressed.
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos and select the best solution.
