Forum Discussion
SivaKona
Occasional Contributor
Occasional Contributorpcie gen3x8 DMA EndPoint with HPTXS path is not meeting timing
Hi , I have generated an FPGA model with PCIe DMA EP and onchip Memory as shown in the attached "DMA_EP_OnchipMem_model.png" file. I have instantiated an Onchip Memory of size 16MB. Seeing Setup...
You may try to lower your clock frequency, with increased in clock period, it is easier to meet setup.
Or you can add pipeline stages. You may checkout the video below
https://www.youtube.com/watch?v=g6SjVhVderc
Wincent_Altera
Regular Contributor
Regular ContributorHi,
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
Best regards,
Wincent_C_Intel
